Ben Feinberg

Ben Feinberg

Senior Member of Technical Staff, Sandia National Laboratories

I am a researcher in the Scalable Computer Architectures department at Sandia National Laboratories. My research focuses on memory-centric and analog accelerators for HPC and ML applications, and energy-efficient and reliable architectures for autonomous systems.

Research interests: analog accelerators, edge/autonomous systems architectures, memory-centric architectures with emerging memories

Education

  • Ph.D. Electrical Engineering, University of Rochester, 2019
  • M.S. Electrical Engineering, University of Rochester, 2014
  • B.S. Electrical Engineering, University of Rochester, 2012

Selected Papers

Ryan Wong, Ben Feinberg, Saugata Ghose
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026
Ben Feinberg, T. Patrick Xiao, Christopher H. Bennett, Sapan Agarwal
IEEE Micro, 2026
Ryan Wong, Nikita Kim, Aniket Das, Kevin Higgs, Engin Ipek, Sapan Agarwal, Saugata Ghose, Ben Feinberg
International Symposium on Computer Architecture (ISCA), 2025
T. Patrick Xiao, Ben Feinberg, David K. Richardson, Matthew Cannon, Calvin Madsen, Harsha Medu, Vineet Agrawal, Matthew J. Marinella, Sapan Agarwal, Christopher H. Bennett
arXiv preprint, 2024
T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella
IEEE Circuits and Systems Magazine, 2022
T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Vineet Agrawal, Prashant Saxena, Venkatraman Prabhakar, Krishnaswamy Ramkumar, Harsha Medu, Vijay Raghavan, Ramesh Chettuvetty, Sapan Agarwal, Matthew J. Marinella
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2022
Ben Feinberg, Ryan Wong, T. Patrick Xiao, Christopher H. Bennett, Jacob N. Rohan, Erik G. Boman, Matthew J. Marinella, Sapan Agarwal, Engin Ipek
International Symposium on High-Performance Computer Architecture (HPCA), 2021
Ben Feinberg, Benjamin C. Heyman, Darya Mikhailenko, Ryan Wong, An C. Ho, Engin Ipek
International Symposium on Computer Architecture (ISCA), 2020
Ben Feinberg, Uday Kumar Reddy Vengalam, Nathan Whitehair, Shibo Wang, Engin Ipek
International Symposium on Computer Architecture (ISCA), 2018
Ben Feinberg, Shibo Wang, Engin Ipek
International Symposium on High-Performance Computer Architecture (HPCA), 2018
★ Honorable Mention for IEEE Micro Top Picks.

Software

CrossSim

CrossSim is a GPU-accelerated accuracy simulator and co-design tool for analog in-memory computing. It models how hardware non-idealities in resistive crossbar arrays — programming errors, conductance drift, read noise, ADC quantization, and parasitic resistance — affect algorithm accuracy across neural network inference, signal processing, and linear algebra workloads. CrossSim provides a NumPy-like API, interfaces for PyTorch and Keras models, and supports hardware-aware training.

SST Elements

The Structural Simulation Toolkit (SST) is a modular parallel simulation framework for exploring innovations in highly concurrent systems, including processors, memory hierarchies, and network interconnects. Within SST Elements, I maintain Golem, a simulation model for analog accelerator tiles, and contribute to Carcosa, a component for modeling heterogeneous compute architectures.